1. Field of the Invention
The present invention relates generally to semiconductor devices and in particular to semiconductor memory architecture.
2. Background of the Invention
Memory cells of dynamic random access memories (DRAMs) are usually designed as one transistor/one capacitor (1T1C) memory cells each having a storage capacitor for storing charge carriers and a selection transistor for addressing the storage capacitor. In the case of memory cells of the “trench capacitor” type, the storage capacitors are arranged in the substrate essentially below a transistor plane formed by the selection transistors and, in the case of memory cells of the “stacked capacitor” type, essentially above the transistor plane.
To increase the performance of DRAMs, both miniaturization of the feature sizes and achieving a smallest possible spacing between memory cells relative to a minimum feature size F is desirable. The minimum feature size may be reduced in lithography-dictated steps, in which case memory cell concepts can be transferred from a larger minimum feature size to a smaller minimum feature size without additional changes beyond shrinking of the memory cell structures to scale. Well-scalable memory cell concepts are advantageous since an additional outlay for changes in a layout of the memory cell structures over and above adaptations that are purely to scale is limited in the event of a transition to a smaller feature size.
A known approach to reducing the space requirement of a memory cell, is to provide the selection transistor in a structure that is vertical with respect to the transistor plane. In this case, the source/drain connection regions (S/D junctions) are arranged essentially vertically one above the other relative to the transistor plane. A channel controlled by a gate electrode of the selection transistor is then formed, principally in a direction perpendicular to the transistor plane, in an active region of the selection transistor which is provided between the two source/drain connection regions of the selection transistor. An architecture having vertical transistor cells is disclosed for example in U.S. Pat. No. 6,352,894 B1 (Goebel et al.) and illustrated in FIG. 1, which is adapted from the Figures of the above patent specification.
FIG. 1 shows a plurality of transistor cells 81 arranged on a substrate 1. In this case, each transistor cell 81 has an upper source/drain connection region 4 and a lower source/drain connection region 2. An active region (also called body region) 3 is in each case formed between upper 4 and lower 2 source/drain connection regions. transistor cells 81 are respectively arranged in rows and columns arranged at right angles to one another, the rows extending along an x direction and the columns extending along a y direction perpendicular to the x direction. Within a row, respectively adjacent transistor cells 81 are separated by narrow isolation trenches 6. Adjacent rows are isolated from one another by wide active trenches 5. First sections of gate electrodes 52 are formed in narrow isolation trenches 6. Two mutually insulated word lines 521, 522 which are respectively assigned to one of the adjacent rows pass through wide active trenches 5, said word lines forming second sections of gate electrodes 52. Gate electrodes 52 respectively arranged in a row are conductively connected to one another via word lines 521, 522. Gate electrode 52 of each transistor cell 81 surrounds active region 3 from four sides. Lower source/drain connection regions 2 of transistor cells 81 are formed as sections of a connection plate (buried plate) 21, which, in an upper region, is patterned by active trenches 5 and isolation trenches 6, and are electrically conductively connected to one another. Gate electrode 52 of a transistor cell 81 is insulated from active region 3 of assigned transistor cell 81 by a gate dielectric 51. An insulator layer 50 insulates source/drain connection regions 2, 4 from adjoining conductive structures and is opened section by section for the connection of the upper source/drain connection regions, for instance to an electrode of a storage capacitor, in the course of a further processing.
A disadvantage of the illustrated architecture of transistor cells 81 is that active regions 3 of transistor cells 81 are electrically without connection.
If, in the operating state of a transistor cell, a channel controlled by a potential at the gate electrode is formed in the active region of the transistor cell, then majority carriers do not flow away from the active region in transistor cells without electrical connection of the active region. However, an accumulation of majority carriers in the active region disadvantageously alters the electrical properties of the transistor cell. In particular, an accumulated charge in the active region can activate a parasitic bipolar transistor which, under specific operating conditions of an architecture of memory cells, may cause a leakage current to or from the source/drain connection region oriented toward the storage capacitor (floating body effect). As a result, a charge stored on the storage capacitor is altered and a datum represented by the charge and stored in the memory cell is corrupted, if the storage capacitor is not recharged within a specified time. Each recharging process increases an average access time to the datum stored in the memory cell and the power consumption of the memory cell.
With the transistor cell architecture illustrated in FIG. 1 it is possible, with a minimum feature size F, to produce memory cells with a planar area requirement of 4 F2, or 8 F2 in the case of memory concepts with a so-called folded bit line structure. An additional connection for the active region of each transistor cell according to a conventional type would considerably increase the area requirement of the transistor cell.